1. Field of the Invention
This invention relates to the field of semiconductor devices, and more specifically, to a process and apparatus for chemical mechanical polishing.
2. Background Information
Integrated circuits manufactured today are made up of literally millions of active devices such as transistors and capacitors formed in a semiconductor substrate. These active devices are formed and interconnected in an elaborate system of layers. A considerable amount of effort in the manufacture of modern complex, high density multilevel interconnections is devoted to the planarization of the individual layers of the interconnect structure. Nonplanar surfaces create poor optical resolution of subsequent photolithographic processing steps. Poor optical resolution prohibits the printing of high density interconnect metal lines. Another problem with nonplanar surface topography is the step coverage of subsequent metallization layers. If a step height is too large there is a serious danger that open circuits will be created. Planar interconnect surface layers are a must in the fabrication of modern high density integrated circuits.
To ensure planar topography, various planarization techniques have been developed. One approach, known as chemical mechanical polishing, employs polishing to remove protruding steps formed along the upper surface of interlayer dielectrics (ILDs). Chemical mechanical polishing is also used to "etch back" conformally deposited metal layers to form planar plugs or vias.
FIG. 1 illustrates a typical chemical mechanical polisher 100. As shown, a substrate (or wafer) 110 is held by a carrier 120. Carrier 120 presses wafer 110 against polishing pad 130 with a downward force. Polishing pad 130 is attached to polishing platen 140. Polishing pad 130 is covered with an active slurry 150 and polishing platen 140 rotates in one direction while carrier 120 rotates in the opposite direction. The downward force, rotational motion, surface of the polishing pad, and slurry act together to polish or planarize the surface of wafer 110.
This type of chemical mechanical polishing however exhibits some problems. For example, such tools have limitations in controlling both components of shear force and downward force applied to a wafer surface. Moreover, as semiconductor devices become smaller and more dense chemical mechanical polishing is causing some problems with newer materials used to fabricate current semiconductor devices. Prior art materials used in conjunction with chemical mechanical polishing have been relatively hard and/or stiff materials such as oxides, polysilicon, etc. As a result, chemical mechanical polishing processes have been optimized for these materials.
New materials, such as materials with low dielectric constants are being used in order to reduce the RC Time Constant in current semiconductor devices. The RC Time Constant is the fundamental limit of a microprocessor caused by the capacitance between the metal lines of the microprocessor. There are two things which determine the RC Time Constant: the resistance of the metal lines themselves and the capacitance of the dielectric materials.
Silicon dioxide, which is widely used as a dielectric material has a dielectric constant (k) of approximately k=4. However, by switching to materials with lower dielectric constants, for example in the range of approximately k=2-3, several advantages may be obtained. The use of low k polymers have been found reduce the RC Time Constant due to a decreased capacitance and therefore increase the speed of the device. The use of low k materials have also been found to reduce power consumption, and reduce crosstalk noise between metal lines.
Unfortunately, low k materials tend to be polymers which are more plastic like materials. Therefore, when polishing such low k materials in chemical mechanical polishing they tend to bend and/or deform, because they are plastic, causing bad results and bad uniformity during planarization. This is especially apparent when comparing the polishing results in areas with densely populated regions of the topography and lightly populated regions of the topography. In other words, where the topography is densely populated the low k materials are less likely to bend under the downward force of the polisher resulting in better polishing uniformity. Whereas, in areas of the topography that are more lightly populated the low k materials are more likely to deform under the downward force of the polisher causing nonuniform results in the polishing process.
FIG. 2 illustrates a low k material after planarization with prior art chemical mechanical polisher and polishing method. As shown, low k material 210 was deposited above metal lines 220 and substrate 200. Since low k material 210 is somewhat plastic it deformed during the chemical mechanical polishing process. As illustrated, because low k material 210 deformed more in the less populated areas of the topography during the polishing process and as a consequence the top surface is not uniform and is not evenly planarized.
Other process issues also arise during chemical mechanical polishing of low k materials. For example, low k materials may interact with the polishing pads and slurries of the chemical mechanical polishing process. As another example, low k materials are mechanically weak and may have poor adhesion (compared to silicon oxides) and therefore may not hold up or adhere to underlying layers through the chemical mechanical polishing process. Additionally, low k materials have a lower thermal stability which may be affected by the friction and higher temperatures of the chemical mechanical polishing process. At higher temperatures low k materials may suffer thermal deformation (and plasticity) due to material heat up.
Thus, what is needed is a chemical mechanical polisher and polishing process that will improve process control over the planarization of low k materials with polishing uniformity and good electrical results regardless of the density of the underlying topography.